The present invention relates to a semiconductor device, and particularly to a technique effective when applied to a semiconductor device having capacitive elements.
Various semiconductor devices have been manufactured by forming MISFETs and capacitors over a semiconductor substrate and coupling between respective elements by wirings.
Japanese Unexamined Patent Publication No. Hei 8 (1996)-306870 (patent document 1) has described a technique wherein capacitances necessary for a step-up circuit are configured by coupling in series one or more MOS capacitive elements or junction capacitance elements using a layer formed upon forming MOS transistors or bipolar elements, and the number of series connections is set to the number at which the voltage applied to each of the MOS capacitance elements and junction capacitance elements is brought to its breakdown voltage or less.